Operation with different size operands in Verilog/SystemVerilog

When an operation such as an addtion or a substraction is done using different size operands than final variable, it is necessary to extend sign to ensure the operation is done properly.

Example:

Wrong:

Sign on data_in will not be respected. data_in will be filled with 0 before doing the operation and won’t be taken as negative (if applies).

Correct:

Extend sign to match number of acc_add bits before doing operation