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## The uvm_object class

The uvm_object class is the base class for all UVM classes. From it, all the rest of classes are extended. It provides basic functionalities such as print, compare, copy and similar methods.

This class can be used when defining reusable parts of a sequence items. For example, in a packet like uvm_sequence_item, we could define a uvm_object extended object for defining the header. This would be:

class packet_header extends uvm_object;

rand bit [2:0] len;

uvm_field_int(len, UVM_DEFAULT)
uvm_object_utils_end

super.new(name);
endfunction : new

endclass : packet_header

This packet_header could be included in a packet class for conforming the uvm_sequence_item (the transaction) which will compose the sequences:

class simple_packet extends uvm_sequence_item;

uvm_object_utils_begin(simple_packet)
uvm_field_object(header, UVM_DEFAULT)
uvm_object_utils_end

function new (string name = "simple_packet");
super.new(name);
endfunction : new

endclass : packet

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## Phases in UVM

UVM introduces the concept of phases to ensure that all objects are properly configured and connected before starting the runtime simulation. Phases contribute to a better synchronised simulation and enable to the verification engineer to get better modularity of the testbench.

UVM phases consists of:

1. build
2. connect
3. end_of_elaboration
4. start_of_simulation
5. run
1. reset
2. configure
3. main
4. shutdown
6. extract
7. check
8. report
9. final

The run phase has been simplified to get a better picture of how phases worked. Nevertheless, all subphases in the run phase have a pre_ and post_ phase to add flexibility. Therefore, the run phase is actually composed by the following phases:

1. run
1. pre_reset
2. reset
3. post_reset
4. pre_configure
5. configure
6. post_configure
7. pre_main
8. main
9. post_main
10. pre_shutdown
11. shutdown
12. post_shutdown

Although all phases play an important role, the most relevant phases are:

• build_phase: objects are created
• connect_phase: interconnection between objects are hooked
• run_phase: the test starts. The run_phase is the only phase which is a task instead of a function, and therefore is the only one that can consume time in the simulation.

UVM phases are executed from a hierarchical point of view from top to down fashion. This means that the first object that executes a phase is the top object, usually

testbench  test  environment agent {monitor, driver, sequencer, etc}

Nevertheless, in the connect phase, this happens the other way round in a down to top fashion.

{monitor, driver, sequencer} agent environment test testbench

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To use UVM in your Verilog test bench, you need to compile the UVM package top. To do so, you need to include it on your file by using:

include "uvm_macros.svh"
include "uvm_pkg.sv"
import uvm_pkg::*;


The uvm_pkg is contained in the uvm_pkg.sv that must be passed to the compiler. Therefore, it is necessary to indicate the UVM path to the compiler. In Cadence Incisive Enterprise Simulator (IES) is as easy as to specify -uvm switch.

In Modelsim, from Modelsim console, run:

vsim -work work +incdir+/path/to/uvm-1.1d/src +define+UVM_CMDLINE_NO_DPI +define+UVM_REGEX_NO_DPI +define+UVM_NO_DPI


After compilation, click on Simulate > Start simulation and select the tb in the work library. Then, run the simulation for the desired time.