How to add UVM in your Verilog test bench

To use UVM in your Verilog test bench, you need to compile the UVM package top. To do so, you need to include it on your file by using:

The uvm_pkg is contained in the that must be passed to the compiler. Therefore, it is necessary to indicate the UVM path to the compiler. In Cadence Incisive Enterprise Simulator (IES) is so easy as to specify -uvm switch.

In Modelsim, from Modelsim console, run:

After compilation, click on Simulate > Start simulation and select the tb in the work library. Then, run the simulation for the desired time.

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