To use UVM in your Verilog test bench, you need to compile the UVM package top. To do so, you need to include it on your file by using:
`include "uvm_macros.svh" import uvm_pkg::*;
uvm_pkg is contained in the uvm_pkg.sv that must be passed to the compiler. Therefore, it is necessary to indicate the UVM path to the compiler. In Cadence Incisive Enterprise Simulator (IES) is as easy as to specify
In Modelsim, from Modelsim console, run:
vsim -work work +incdir+/path/to/uvm-1.1d/src +define+UVM_CMDLINE_NO_DPI +define+UVM_REGEX_NO_DPI +define+UVM_NO_DPI
After compilation, click on Simulate > Start simulation and select the tb in the work library. Then, run the simulation for the desired time.